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Low Phase Noise, High-frequency Radio Synchronizers and JESD204B/C Clock Jitter Attenuators for 4G/5G Radio EVM Performance
Renesas Electronics Corporation has introduced a new 8V19N850 radio synchronizer and 8V19N880, 8V19N882 JESD204B/C clock jitter attenuators for delivering ITU-T compliant network clock synchronization, best-in-class phase noise, and high clock frequency. These three new low phase noise, high-frequency RF timing solutions were designed for 4G and 5G radio, and there are two new Winning Combinations to address the need for full signal chain solutions.
The new integrated 5G radio synchronization solution, 8V19N850 radio synchronizer is equipped with a complete set of features for radio synchronization on a single chip; including full ITU-T G.8273.2 T-BC/T-TSC Class C, ITU-T G.8262.1 enhanced SyncE, and JESD204B/C compliance. The device also takes care of recovering the clock from CPRI/eCPRI, per IEEE 802.1cm fronthaul synchronization requirements; hence they are suitable for use in emerging 5G O-RAN networks for Radio Units (O-RU).
For various mission-critical industrial data converter applications in wireless radio, test & measurement, instrumentation, and high-performance imaging the new 8V19N880 and 8V19N882 JESD204B/C clock jitter attenuators can deliver low phase noise and exceptional jitter performance as low as 74fs RMS and -90dB spurious attenuation. By supporting frequencies up to 3932.16 MHz (up to 6 GHz with an external VCO) and featuring 16 and 18 integrated differential outputs, the device can put together high performance, low voltage, and low power consumption with 1.8V support.
These new devices feature two new Winning Combinations that were designed to address the increasing demand for higher bandwidth for cellular services. The Small Cell Radio and MIMO Radio solutions use mutually compatible devices for lower risk and faster time to market. They deliver the combined benefits of new RF timing ICs paired with Renesas’ complementary microcontroller and power management offerings to accelerate solution design.
Features of 8V19N850 Radio Synchronizer
- Digital clock domain (Ethernet, FEC) with support for eEEC and T-BC/T-TSC Class C
- 2 differential clock reference inputs with 1PPS (1Hz) to 1GHz input frequency
- External control of the DCO for IEEE1588
- Digital holdover with a 1.1 × 10-7 ppb accuracy
- Programmable DPLL loop bandwidth 1mHz - 6kHz
- Configurable phase delay (range: 1UI)
- Hitless input switching with < 1ns output phase error
- 1 external synchronization input for JESD204B/C (LVCMOS)
- 16 differential outputs
- Optimized for low phase noise: -146dBc/Hz (1MHz offset; 245.76MHz clock)
- Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V
- Board temperature range: -40°C to +105°C
Features of 8V19N880 and 8V19N882 JESD204B/C Clock Jitter Attenuators
- High-performance clock RF sampling clock generator and clock jitter attenuator with support for JESD204B/C
- Low phase noise: -144.7dBc/Hz (800kHz offset; 491.52MHz)
- Integrated phase noise of 74fs RMS (12kHz–20MHz, 491.52MHz)
- Dual-PLL architecture with internal and optional external VCO
- Eight output channels with a total of 18 outputs
- Clock output frequencies: up to 3932.16MHz (internal VCO) and 6GHz (optional external VCO)
- Differential, low noise I/O
- SPI 3/4 wire configuration interface
- Supply voltage: 1.8V (core, outputs) and 3.3V (high-performance outputs)
Note: More technical information can be found in the 8V19N850D Datasheet linked at the bottom of this page and in the product pages of 8V19N850 radio synchronizer, 8V19N880, and 8V19N882 JESD204B/C clock jitter attenuators.
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