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Infineon Launches Groundbreaking LPDDR Flash Memory Solution for Automotive Industry

SEMPER X1LPDDR Flash Memory
SEMPER X1LPDDR Flash Memory

Infineon Technologies has launched a groundbreaking LPDDR Flash memory solution, SEMPER X1, for next-generation automotive E/E architectures. The device delivers safe, reliable, and real-time code execution, which is critical for automotive domain and zone controllers. With the ever-increasing intelligence, connectivity, complexity the next-generation vehicles need to rely on advanced manufacturing processes and multi-core processors to meet these high demanding requirements. Higher density embedded non-volatile memories are no longer a cost-effective option at these advanced nodes. Thus, system architects need to consider using external NOR for code storage. However, current memories available on the market cannot meet the performance demands of complex automotive real-time processors. Infineon's SEMPER X1 is a solution to this problem, offering eight times the performance of current NOR Flash memories and achieving 20 times faster random read transactions for real-time applications. SEMPER X1 is ISO26262 ASIL-B compliant, offering advanced error correction and other safety features. Infineon SEMPER X1 is now in the sampling phase and will be commercially available in 2024. Infineon is excited to collaborate with industry partners to drive standardization of the memory and bring it to broader markets.

 

Applications

  • Safe, reliable and real-time code execution for automotive domain and zone controllers
  • 8 times the performance of current NOR Flash memories
  • 20 times faster random read transactions for real-time applications
  • Enables software-defined vehicles to deliver advanced features with enhanced safety and architectural flexibility
  • LPDDR4 interface operating at 3.2 GBytes/sec
  • Multi-bank architecture to meet the performance and density requirements of domain and zone controllers
  • Real-time execute-in-place (XiP) memory
  • Scales independently of the processor

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